Freescale Semiconductor, Inc.
FLASH-1 Memory
FLASH-1 Control Register
The row architecture for this array is:
• $8000–$803F (Row 0)
• $8040–$807F (Row 1)
• $8080–$80BF (Row 2)
• --------------------------------------
• $FFC0–$FFFF (Row 511)
Programming tools are available from Motorola. Contact a local Motorola
representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.(1)
4.4 FLASH-1 Control Register
The FLASH-1 control register (FLCR1) controls FLASH-1 program,
erase, and margin read operations.
Address: $FE0B
Bit 7
FDIV1
0
6
FDIV0
0
5
BLK1
0
4
BLK0
0
3
2
1
Bit 0
PGM
0
Read:
Write:
Reset:
HVEN MARGIN ERASE
0
0
0
Figure 4-1. FLASH-1 Control Register (FLCR1)
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the factor by which the
charge pump clock is divided from the system clock. See 4.5 FLASH
Charge Pump Frequency Control.
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the factor by which the
charge pump clock is divided from the system clock. See 4.5 FLASH
Charge Pump Frequency Control.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908AS60 — Rev. 1.0
Technical Data
FLASH-1 Memory
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
