Freescale Semiconductor, Inc.
FLASH-1 Memory
7. Wait for a time, tKill, for the high voltages to dissipate.
8. Clear the ERASE bit.
9. After time tHVD, the memory can be accessed in read mode again.
NOTE: While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
Table 4-2 shows the various block sizes which can be erased in one
erase operation.
Table 4-2. Erase Block Sizes
BLK1
BLK0
Block Size, Addresses Cared
Full array: 30 Kbytes
0
0
1
1
0
1
0
1
One-half array: 16 Kbytes (A14)
Eight rows: 512 bytes (A14–A9)
Single row: 64 bytes (A14–A6)
In step 2 of the erase operation, the cared addresses are latched and
used to determine the location of the block to be erased. For instance,
with BLK0 = BLK1 = 0, writing to any FLASH address in the range
$8000–$FFFF will enable the full-array erase.
NOTE: To ensure the timing requirements of the high-voltage erase and
program mode of the FLASH memory, interrupts must be masked
(interrupt mask bit of CCR = 1) when the HVEN bit is set.
4.7 FLASH Program/Margin Read Operation
NOTE: After a total of eight program operations have been applied to a row, the
row must be erased before further programming to avoid program
disturb. An erased byte will read $00.
Programming of the FLASH memory is done on a page basis. A page
consists of eight consecutive bytes starting from address $XXX0 or
$XXX8. The purpose of the margin read mode is to ensure that data has
been programmed with sufficient margin for long-term data retention.
While performing a margin read, the operation is the same as for
Technical Data
MC68HC908AS60 — Rev. 1.0
FLASH-1 Memory
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