Freescale Semiconductor, Inc.
FLASH-1 Memory
4.3 Functional Description
The FLASH memory physically consists of two independent arrays of
32 Kbytes with an additional 38 bytes of user vectors and two bytes of
block protection. An erased bit reads as a logic 0 and a programmed bit
reads as a logic 1. Program and erase operations are facilitated through
control bits in a memory mapped register. Details for these operations
appear later in this section. Memory in the FLASH array is organized into
pages within rows. There are eight pages of memory per row with eight
bytes per page. The minimum erase block size is a single row, 64 bytes.
Programming is performed on a per-page basis, eight bytes at a time.
The FLASH-1 address ranges for the user memory, control register, and
vectors are:
• $8000–$FDFF
• $FF80–$FF81, block protect registers
• $FE0B, FLASH control register
• $FFDA–$FFFF, reserved for user-defined interrupt and reset
vectors
When programming the FLASH, just enough program time must be used
to program a page. Too much program time can result in a program
disturb condition, in which case an erased bit on the row being
programmed becomes unintentionally programmed. Program disturb is
avoided by using an iterative program and margin read technique known
as the smart programming algorithm. The smart programming algorithm
is required whenever programming the FLASH (see 4.7 FLASH
Program/Margin Read Operation).
To avoid the program disturb issue, each page on the row should be
programmed only once before it is erased. The eight program cycle
maximum per row aligns with the architecture’s eight pages of storage
per row. The margin read step of the smart programming algorithm is
used to ensure programmed bits are programmed to sufficient margin for
data retention over the device lifetime.
Technical Data
MC68HC908AS60 — Rev. 1.0
FLASH-1 Memory
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
