Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving CGMOUT, this
read/write bit can indicate whether the crystal reference frequency is
active or not.
1 = Crystal reference not active
0 = Crystal reference active
To check the status of the crystal reference:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. N is the VCO frequency multiplier.
3. Read XLD.
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
Bits 3–0 — Reserved for Test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write 0s to bits 3–0 when writing to PBWC.
Technical Data
MC68HC908AS60 — Rev. 1.0
Clock Generator Module (CGM)
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