Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
fVRS. (See 10.4.2.1 Circuits, 10.4.2.4 Programming the PLL, and
10.6.1 PLL Control Register.) VRS7–VRS4 cannot be written when
the PLLON bit in the PLL control register (PCTL) is set. See 10.4.2.5
Special Programming Exceptions. A value of $0 in the VCO range
select bits disables the PLL and clears the BCS bit in the PCTL. (See
10.4.3 Base Clock Selector Circuit and 10.4.2.5 Special
Programming Exceptions for more information.) Reset initializes
the bits to $6 to give a default range multiply value of 6.
NOTE: The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
10.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupt requests from the PLL. PLLF, the interrupt flag in the
PCTL, becomes set whether CPU interrupt requests are enabled or not.
When the AUTO bit is clear, CPU interrupt requests from the PLL are
disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to
see if the request was due to an entry into lock or an exit from lock. When
the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
CPU interrupt requests should be disabled to prevent PLL interrupt
Technical Data
MC68HC908AS60 — Rev. 1.0
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
