Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM Registers
10.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Address: $001D
Bit 7
AUTO
0
6
5
ACQ
0
4
XLD
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
LOCK
0
0
0
0
0
= Unimplemented
Figure 10-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
MC68HC908AS60 — Rev. 1.0
Technical Data
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
