Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Low-Power Modes
service routines from impeding software performance or from exceeding
stack limitations.
NOTE: Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
10.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
10.8.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
10.8.2 Stop Mode
The STOP instruction disables the CGM and holds low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If CGMOUT is being driven by CGMVCLK and a STOP instruction is
executed, the PLL will clear the BCS bit in the PLL control register,
causing CGMOUT to be driven by CGMXCLK. When the MCU recovers
from STOP, the crystal clock divided by two drives CGMOUT and BCS
remains clear.
10.9 CGM During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. See Section 12. Break
Module.
MC68HC908AS60 — Rev. 1.0
Technical Data
Clock Generator Module (CGM)
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