Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
10.5.4 Analog Power Pin (VDDA
)
VDDA is a power pin used by the analog portions of the PLL. Connect the
VDDA pin to the same voltage potential as the VDD pin.
NOTE: Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
10.5.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal enables the oscillator and PLL.
10.5.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (fXCLK) and comes directly from the crystal oscillator circuit.
Figure 10-3 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
10.5.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate
the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at
twice the bus frequency. CGMOUT is software programmable to be
either the oscillator output, CGMXCLK, divided by two or the VCO clock,
CGMVCLK, divided by two.
10.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the CPU interrupt signal generated by the PLL lock detector.
Technical Data
MC68HC908AS60 — Rev. 1.0
Clock Generator Module (CGM)
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