Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
5. Calculate the bus frequency, fBUS, and compare fBUS with
fBUSDES
.
fVCLK
fBUS = -------------
4
32 MHz
Example: fBUS= -------------------- = 8 MHz
4
6. If the calculated fBUS is not within the tolerance limits of the
application, select another fBUSDES or another fRCLK
.
7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
fVCLK
L = round ------------
fNOM
32 MHz
Example: L =
= 7
-------------------------------
4.9152 MHz
8. Calculate the VCO center-of-range frequency, fVRS. The
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
fVRS = L × fNOM
Example: fVRS = 7 × 4.9152 MHz = 34.4 MHz
fNOM
----------------
NOTE: For proper operation, fVRS – fVCLK
≤
.
2
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
Technical Data
MC68HC908AS60 — Rev. 1.0
Clock Generator Module (CGM)
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