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MC68HC908AS60CFU 参数 Datasheet PDF下载

MC68HC908AS60CFU图片预览
型号: MC68HC908AS60CFU
PDF下载: 下载PDF文件 查看货源
内容描述: HCMOS微控制器单元 [HCMOS Microcontroller Unit]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 454 页 / 5714 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Clock Generator Module (CGM)  
Functional Description  
10.4.2.2 Acquisition and Tracking Modes  
The PLL filter is manually or automatically configurable into one of two  
operating modes:  
1. Acquisition mode — In acquisition mode, the filter can make large  
frequency corrections to the VCO. This mode is used at PLL  
startup or when the PLL has suffered a severe noise hit and the  
VCO frequency is far off the desired frequency. When in  
acquisition mode, the ACQ bit is clear in the PLL bandwidth control  
register. See 10.6.2 PLL Bandwidth Control Register.  
2. Tracking mode — In tracking mode, the filter makes only small  
corrections to the frequency of the VCO. PLL jitter is much lower  
in tracking mode, but the response to noise is also slower. The  
PLL enters tracking mode when the VCO frequency is nearly  
correct, such as when the PLL is selected as the base clock  
source. See 10.4.3 Base Clock Selector Circuit. The PLL is  
automatically in tracking mode when it’s not in acquisition mode or  
when the ACQ bit is set.  
10.4.2.3 Manual and Automatic PLL Bandwidth Modes  
The PLL can change the bandwidth or operational mode of the loop filter  
manually or automatically.  
In automatic bandwidth control mode (AUTO = 1), the lock detector  
automatically switches between acquisition and tracking modes.  
Automatic bandwidth control mode also is used to determine when the  
VCO clock, CGMVCLK, is safe to use as the source for the base clock,  
CGMOUT. See 10.6.2 PLL Bandwidth Control Register. If PLL CPU  
interrupt requests are enabled, the software can wait for a PLL CPU  
interrupt request and then check the LOCK bit. If CPU interrupts are  
disabled, software can poll the LOCK bit continuously (during PLL  
startup, usually) or at periodic intervals. In either case, when the LOCK  
bit is set, the VCO clock is safe to use as the source for the base clock.  
See 10.4.3 Base Clock Selector Circuit. If the VCO is selected as the  
source for the base clock and the LOCK bit is clear, the PLL has suffered  
a severe noise hit and the software must take appropriate action,  
depending on the application. See 10.7 Interrupts.  
MC68HC908AS60 — Rev. 1.0  
Technical Data  
Clock Generator Module (CGM)  
For More Information On This Product,  
Go to: www.freescale.com  
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