Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
These conditions apply when the PLL is in automatic bandwidth control
mode:
• The ACQ bit (see 10.6.2 PLL Bandwidth Control Register) is a
read-only indicator of the mode of the filter. See 10.4.2.2
Acquisition and Tracking Modes.
• The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆TRK, and is cleared when the VCO frequency is out of
a certain tolerance, ∆UNT. See 24.2 Maximum Ratings.
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆Lock, and is cleared when the VCO frequency is out of
a certain tolerance, ∆unl. See 24.2 Maximum Ratings.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. See 10.6.1 PLL
Control Register.
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below fBUSMAX
and require fast startup.
These conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, tacq (see 24.2 Maximum Ratings), after turning on the
PLL by setting PLLON in the PLL control register (PCTL).
• Software must wait a given time, tAL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
Technical Data
MC68HC908AS60 — Rev. 1.0
Clock Generator Module (CGM)
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