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MC68HC908AS60CFU 参数 Datasheet PDF下载

MC68HC908AS60CFU图片预览
型号: MC68HC908AS60CFU
PDF下载: 下载PDF文件 查看货源
内容描述: HCMOS微控制器单元 [HCMOS Microcontroller Unit]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 454 页 / 5714 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Clock Generator Module (CGM)  
The operating range of the VCO is programmable for a wide range of  
frequencies and for maximum immunity to external noise, including  
supply and CGMXFC noise. The VCO frequency is bound to a range  
from roughly one-half to twice the center-of-range frequency, fVRS  
.
Modulating the voltage on the CGMXFC pin changes the frequency  
within this range. By design, fVRS is equal to the nominal center-of-range  
frequency, fNOM, (4.9152 MHz) times a linear factor L or (L)fNOM  
.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.  
CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a  
buffer. The buffer output is the final reference clock, CGMRDV, running  
at a frequency fRDV = fRCLK  
.
The VCO’s output clock, CGMVCLK, running at a frequency fVCLK, is fed  
back through a programmable modulo divider. The modulo divider  
reduces the VCO clock by a factor, N. The divider’s output is the VCO  
feedback clock, CGMVDV, running at a frequency fVDV = fVCLK/N. See  
10.4.2.4 Programming the PLL for more information.  
The phase detector then compares the VCO feedback clock, CGMVDV,  
with the final reference clock, CGMRDV. A correction pulse is generated  
based on the phase difference between the two signals. The loop filter  
then slightly alters the dc voltage on the external capacitor connected to  
CGMXFC based on the width and direction of the correction pulse. The  
filter can make fast or slow corrections depending on its mode, as  
described in 10.4.2.2 Acquisition and Tracking Modes. The value of  
the external capacitor and the reference frequency determines the  
speed of the corrections and the stability of the PLL.  
The lock detector compares the frequencies of the VCO feedback clock,  
CGMVDV, and the final reference clock, CGMRDV. Therefore, the  
speed of the lock detector is directly proportional to the final reference  
frequency, fRDV. The circuit determines the mode of the PLL and the lock  
condition based on this comparison.  
Technical Data  
MC68HC908AS60 — Rev. 1.0  
Clock Generator Module (CGM)  
For More Information On This Product,  
Go to: www.freescale.com  
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