Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
Addr.
Register Name
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLL Control Register
$001C
(PCTL) Write:
See page 169.
Reset:
Read:
0
1
0
1
0
1
0
1
0
LOCK
PLL Bandwidth Control
AUTO
0
ACQ
0
XLD
0
$001D
$001E
Register (PBWC) Write:
See page 171.
Reset:
0
MUL6
1
0
VRS7
0
0
VRS6
1
0
VRS5
1
0
VRS4
0
Read:
PLL Programming Register
MUL7
0
MUL5
1
MUL4
0
(PPG) Write:
See page 173.
Reset:
= Unimplemented
Figure 10-2. I/O Register Summary
10.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
10.4.2.1 Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
MC68HC908AS60 — Rev. 1.0
Technical Data
Clock Generator Module (CGM)
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