Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
10.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .175
10.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .176
10.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .176
10.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .177
10.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . .178
10.2 Introduction
The clock generator module (CGM) generates the crystal clock signal,
CGMXCLK, which operates at the frequency of the crystal. The CGM
also generates the base clock signal, CGMOUT, from which the system
clocks are derived. CGMOUT is based on either the crystal clock divided
by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
The PLL is a frequency generator designed for use with 1-MHz to 8-MHz
crystals or ceramic resonators. The PLL can generate an 8-MHz bus
frequency without using a 32-MHz crystal.
10.3 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of the
crystal reference
• Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
Technical Data
MC68HC908AS60 — Rev. 1.0
Clock Generator Module (CGM)
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