Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
System initialization
3.5.2.7 TMSK2 — Timer interrupt mask register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Timer interrupt mask 2 (TMSK2) $0024 TOI
RTII PAOVI PAII
0
0
PR1 PR0 0000 0000
PR[1:0] are time-protected control bits and can be changed only once
and then only within the first 64 bus cycles after reset in normal modes.
NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
TOI — Timer overflow interrupt enable
1 = Interrupt requested when TOF is set.
0 = TOF interrupts disabled.
RTII — Real-time interrupt enable
1 = Interrupt requested when RTIF set.
0 = RTIF interrupts disabled.
PAOVI — Pulse accumulator overflow interrupt enable (Refer to Timing
System)
1 = Interrupt requested when PAOVF set.
0 = PAOVF interrupts disabled.
PAII — Pulse accumulator interrupt enable (Refer to Timing System)
1 = Interrupt requested when PAIF set.
0 = PAIF interrupts disabled.
PR[1:0] — Timer prescaler select
These two bits select the prescale rate for the main 16-bit free-running
timer system. These bits can be written only once during the first 64
E clock cycles after reset in normal modes, or at any time in special
modes. Refer to the following table:
Prescale
PR[1:0]
factor
0 0
0 1
1 0
1
4
8
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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