Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
3.5.2.5 OPT2 — System configuration options register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
STRC
H
System config. options 2 (OPT2) $0038 LIRDV CWOM
IRVNE LSBF SPR2
0
0
000x 0000
LIRDV — LIR driven
1 = Enable LIR drive high pulse.
0 = LIR only driven low (requires pull-up on pin).
In single chip and bootstrap modes, this bit has no meaning or effect.
The LIR pin is normally configured for wired-OR operation (only pulls
low). In order to detect consecutive instructions in a high-speed
application, this signal can be made to drive high for a quarter of a
cycle to prevent false triggering.
CWOM — Port C wired-OR mode
1 = Port C outputs are open-drain.
0 = Port C operates normally.
STRCH — Stretch external accesses
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
When this bit is set, off-chip accesses of addresses $0000–$7FFF
($8000–$FFFF, if ROMAD is clear) are extended by one E clock cycle
to allow access to slow peripherals. The E clock stretches externally,
but the internal clocks are not affected, so that timers and serial
systems are not corrupted. In single chip and boot modes this bit has
no effect.
IRVNE — Internal read visibility/not E
IRVNE can be written once in any user mode. In expanded modes,
IRVNE determines whether IRV is on or off. In special test mode,
IRVNE is reset to one. In all other modes, IRVNE is reset to zero.
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
Technical Data
MC68HC11P2 — Rev 1.0
Operating Modes and On-Chip Memory
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