Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
EPROM, EEPROM and CONFIG register
3.6.2.1 PPROG — EEPROM programming control register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EEPROM programming
ERAS
E
EEPG
M
$003B ODD EVEN
0
BYTE ROW
EELAT
0000 0000
(PPROG)
NOTE: Writes to EEPROM addresses are inhibited while EEPGM is one. A write
to a different EEPROM location is prevented while a program or erase
operation is in progress.
ODD — Program odd rows in half of EEPROM (Test)
EVEN — Program even rows in half of EEPROM (Test)
If both ODD and EVEN are set to one then all odd and even rows in
half of the EEPROM will be programmed with the same data, within
one programming cycle.
Bit 5 — Not implemented; always reads zero.
BYTE — EEPROM byte erase mode
1 = Erase only one byte of EEPROM.
0 = Row or bulk erase mode used.
ROW — EEPROM row/bulk erase mode (only valid when BYTE = 0)
1 = Erase only one 16 byte row of EEPROM.
0 = Erase all 640 bytes of EEPROM.
Table 3-8. Erase mode selection
Byte
Row
Action
Bulk erase (all 640 bytes)
Row erase (16 bytes)
Byte erase
0
0
1
1
0
1
0
1
Byte erase
ERASE — Erase/normal control for EEPROM
1 = Erase mode.
0 = Normal read or program mode.
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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