Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
System initialization
In single chip modes this bit determines whether the E clock drives
out from the chip.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
Refer to the following table for a summary of the operation
immediately following reset.
IRVNE
E clock
IRV
IRVNE
IRVNE
Mode
after reset after reset after reset affects only can be written
Single chip
Expanded
Boot
0
0
0
1
On
On
On
On
Off
Off
Off
On
E
IRV
E
Once
Once
Once
Special test
IRV
Unlimited
LSBF — LSB-first enable (refer to Serial Peripheral Interface (SPI))
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
SPR2 — SPI clock rate select (refer to Serial Peripheral Interface
(SPI))
This bit adds a divide-by-four to the SPI clock chain.
Bits 1, 0 — not implemented; always read zero.
3.5.2.6 BPROT — Block protect register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PTCO
Block protect (BPROT)
$0035 BULKP
0
BPRT4
BPRT3BPRT2BPRT1BPRT0 1011 1111
N
BPROT prevents accidental writes to EEPROM and the CONFIG
register. The bits in this register can be written to zero only once during
the first 64 E clock cycles after reset in the normal modes; they can be
set at any time. Once the bits are cleared, the EEPROM array and the
CONFIG register can be programmed or erased. Setting the bits in the
BPROT register to logic one protects the EEPROM and CONFIG
Table 3-7
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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