Parallel Host Interface (HDI08) Timing
3.11 Parallel Host Interface (HDI08) Timing
Table 3-15 Host Interface (HDI08) Timing1, 2, 3
150 MHz
No.
Characteristics
Expression
Unit
Min
Max
317 Read data strobe assertion width4
HACK read assertion width
TC + 9.9
—
16.7
—
ns
318 Read data strobe deassertion width4
HACK read deassertion width
9.9
—
—
ns
ns
,
319 Read data strobe deassertion width4 after “Last Data Register” reads5 6, or 2.5 × TC + 6.6
23.3
between two consecutive CVR, ICR, or ISR reads7
HACK deassertion width after “Last Data Register” reads5, 6
320 Write data strobe assertion width8
HACK write assertion width
—
13.2
—
ns
ns
321 Write data strobe deassertion width8
HACK write deassertion width
• after ICR, CVR and “Last Data Register” writes5
2.5 × TC + 6.6
23.3
16.5
—
—
• after IVR writes, or
• after TXH:TXM writes (with HBE=0), or
• after TXL:TXM writes (with HBE=1)
322 HAS assertion width
—
—
—
9.9
0.0
9.9
—
—
—
ns
ns
ns
323 HAS deassertion to data strobe assertion9
324 Host data input setup time before write data strobe deassertion8
Host data input setup time before HACK write deassertion
325 Host data input hold time after write data strobe deassertion8
Host data input hold time after HACK write deassertion
—
—
—
—
—
3.3
3.3
—
—
—
ns
ns
ns
ns
ns
326 Read data strobe assertion to output data active from high impedance4
HACK read assertion to output data active from high impedance
327 Read data strobe assertion to output data valid4
HACK read assertion to output data valid
24.2
9.9
—
328 Read data strobe deassertion to output data high impedance4
HACK read deassertion to output data high impedance
—
329 Output data hold time after read data strobe deassertion4
Output data hold time after HACK read deassertion
3.3
330 HCS assertion to read data strobe deassertion4
331 HCS assertion to write data strobe deassertion8
TC +9.9
—
16.7
9.9
—
—
ns
ns
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-31
FREESCALE [ Freescale ]
