External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, Three Wait States1, 2, 3 (continued)
100 MHz
No.
Characteristics
Symbol
Expression4
Unit
Min
Max
18.0
—
153 RD assertion to data valid
tGA
tGZ
2.5 × TC − 7.0
—
ns
ns
ns
ns
154 RD deassertion to data not valid6
155 WR assertion to data active
0.0
0.75 × TC − 0.3 7.2
0.25 × TC
—
156 WR deassertion to data high impedance
—
2.5
1
2
3
4
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56367.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 × TC for
read-after-read or write-after-write sequences).
5
6
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of
page-access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ
.
Table 3-10 DRAM Page Mode Timings, Four Wait States1, 2, 3
100 MHz
Min Max
No.
Characteristics
Symbol
Expression4
Unit
131 Page mode cycle time for two consecutive accesses of the
same direction
tPC
ns
5 × TC
50.0
45.0
—
—
Page mode cycle time for mixed (read and write) accesses
4.5 × TC
132 CAS assertion to data valid (read)
tCAC
tAA
2.75 × TC − 5.7
3.75 × TC − 5.7
—
—
21.8
31.8
—
ns
ns
ns
ns
ns
ns
133 Column address valid to data valid (read)
134 CAS deassertion to data not valid (read hold time)
135 Last CAS assertion to RAS deassertion
136 Previous CAS deassertion to RAS deassertion
137 CAS assertion pulse width
tOFF
tRSH
tRHCP
tCAS
tCRP
0.0
3.5 × TC − 4.0
6 × TC − 4.0
31.0
56.0
21.0
—
—
2.5 × TC − 4.0
—
138 Last CAS deassertion to RAS assertion5
• BRW[1–0] = 00, 01—Not applicable
• BRW[1–0] = 10
—
—
—
—
—
—
ns
ns
5.25 × TC − 6.0
7.25 × TC − 6.0
46.5
66.5
• BRW[1–0] = 11
139 CAS deassertion pulse width
tCP
2 × TC − 4.0
TC − 4.0
16.0
6.0
—
—
ns
ns
140 Column address valid to CAS assertion
tASC
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-17
FREESCALE [ Freescale ]
