Reset, Stop, Mode Select, and Interrupt Timing
3.9
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1
No.
Characteristics
Expression
Min
Max
Unit
8
9
Delay from RESET assertion to all pins at reset value2
—
—
26.0
ns
Required RESET duration3
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Power on, Internal oscillator
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
333.4
6.7
—
—
—
—
—
—
ns
µs
µs
µs
ns
ns
500
• During STOP, XTAL disabled
500
• During STOP, XTAL enabled
16.7
16.7
• During normal operation
2.5 × TC
10 Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)4
ns
• Minimum
• Maximum
3.25 × TC + 2.0
20.25 × TC + 10
23.7
—
—
145.0
11 Syn reset setup time from RESET
• Maximum
ns
ns
TC
—
6.7
12 Syn reset deassert delay time
• Minimum
3.25 × TC + 1.0
20.25 × TC + 5.0
22.7
—
—
• Maximum
140.0
13 Mode select setup time
30.0
0.0
4.4
4.4
—
—
—
—
ns
ns
ns
ns
ns
14 Mode select hold time
15 Minimum edge-triggered interrupt request assertion width
16 Minimum edge-triggered interrupt request deassertion width
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory access address out valid
• Caused by first interrupt instruction fetch
4.25 × TC + 2.0
7.25 × TC + 2.0
30.3
50.3
—
—
• Caused by first interrupt instruction execution
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution
10 × TC + 5.0
71.7
—
ns
ns
ns
19 Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for level
sensitive fast interrupts5, 6, 7
(WS + 3.75) × TC – 10.94
—
Note 8
Note 8
20 Delay from RD assertion to interrupt request deassertion for (WS + 3.25) × TC – 10.94
—
level sensitive fast interrupts5, 6, 7
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-7
FREESCALE [ Freescale ]
