AC Electrical Characteristics
3
This characteristic does not apply to PCAP.
4
The Appendix A, "Power Consumption Benchmark" section provides a formula to compute the estimated current
requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float).
Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are
90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is
measured with VCCQL = 1.8V, VCC(other) = 3.3V at TJ = 25°C. Maximum internal supply current is measured with VCCQL = 1.89V,
VCC(other) = 3.46V at TJ = 95°C.
5
6
In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to
float).
Periodically sampled and not 100% tested
3.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum
IL
of 0.4 V and a V minimum of 2.4 V for all pins except EXTAL. AC timing specifications, which are
IH
referenced to a device input signal, are measured in production with respect to the 50% point of the
respective input signal’s transition. DSP56367 output levels are measured with the production test machine
V
and V reference levels set at 0.4 V and 2.4 V, respectively.
OL
OH
NOTE
Although the minimum value for the frequency of EXTAL is 0 MHz, the
device AC test conditions are 15 MHz and rated speed.
3.6
Internal Clocks
Table 3-4 Internal Clocks
Expression1, 2
Characteristics
Symbol
Min
—
Typ
(Ef × MF)/(PDF × DF)
Ef/2
Max
—
Internal operation frequency with PLL enabled
Internal operation frequency with PLL disabled
f
f
—
—
Internal clock high period
• With PLL disabled
TH
—
ETC
—
—
• With PLL enabled and MF ≤ 4
0.49 × ETC × PDF ×
0.51 × ETC × PDF ×
DF/MF
DF/MF
• With PLL enabled and MF > 4
0.47 × ETC × PDF ×
—
0.53 × ETC × PDF ×
DF/MF
DF/MF
Internal clock low period
• With PLL disabled
TL
—
ETC
—
—
• With PLL enabled and MF ≤ 4
0.49 × ETC × PDF ×
0.51 × ETC × PDF ×
DF/MF
DF/MF
• With PLL enabled and MF > 4
0.47 × ETC × PDF ×
—
0.53 × ETC × PDF ×
DF/MF
DF/MF
Internal clock cycle time with PLL enabled
TC
—
ETC × PDF × DF/MF
—
DSP56367 Technical Data, Rev. 2.1
3-4
Freescale Semiconductor
FREESCALE [ Freescale ]
