Clock
Table 1-3. Grounds
Ground Name
Description
GND
GND
GND
Bus Control Ground
N
H
S
Isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Host Ground
Isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other chip ground connections.
The user must provide adequate external decoupling capacitors.
ESSI, SCI, and Timer Ground
Isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Note:
These designations are package-dependent. Some packages connect all GND inputs except GND and GND to each other
P P1
internally. On those packages, all ground connections except GND and GND are labeled GND.
P
P1
1.3 Clock
Table 1-4. Clock Signals
State During
Reset
Signal Name
Type
Signal Description
EXTAL
XTAL
Input
Input
External Clock/Crystal Input
Interfaces the internal crystal oscillator input to an external crystal or an
external clock.
Output
Chip-driven
Crystal Output
Connects the internal crystal oscillator output to an external crystal. If an
external clock is used, leave XTAL unconnected.
1.4 Phase Lock Loop (PLL)
Table 1-5. Phase Lock Loop Signals
State During
Reset
Signal Name
Type
Signal Description
CLKOUT
Output
Chip-driven
Clock Output
Provides an output clock synchronized to the internal core clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
PCAP
Input
Input
PLL Capacitor
Connects an off-chip capacitor to the PLL filter. Connect one capacitor
terminal to PCAP and the other terminal to V
.
CCP
If the PLL is not used, PCAP can be tied to V , GND, or left floating.
CC
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-5