Signals/Connections
1.1 Power
Table 1-2. Power Inputs
Power Name
Description
V
V
V
V
V
V
V
PLL Power
Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided
CCP
CCQ
CCA
CCD
CCN
CCH
CCS
with an extremely low impedance path to the V power rail.
CC
Quiet Power
Isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
Address Bus Power
Isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.
Data Bus Power
Isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
Bus Control Power
Isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors.
Host Power
Isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
ESSI, SCI, and Timer Power
Isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
Note:
These designations are package-dependent. Some packages connect all V inputs except V
to each other internally. On
CC
CCP
those packages, all power input except V
are labeled V
.
CCP
CC
1.2 Ground
Table 1-3. Grounds
Ground Name
Description
GND
PLL Ground
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.
should be bypassed to GND by a 0.47 μF capacitor located as close as possible to the chip package.
P
V
CCP
P
GND
GND
PLL Ground 1
P1
Q
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.
Quiet Ground
Isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
GND
GND
Address Bus Ground
A
D
Isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external decoupling capacitors.
Data Bus Ground
Isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
DSP56301 Technical Data, Rev. 10
1-4
Freescale Semiconductor
FREESCALE [ Freescale ]
