Signals/Connections
Signal Name
Table 1-8. External Bus Control Signals (Continued)
State During
Type
Signal Description
Reset
BB
Input/
Output
Input
Bus Busy
Indicates that the bus is active and must be asserted and deasserted
synchronous to CLKOUT. Only after BB is deasserted can the pending bus
master become the bus master (and then assert the signal again). The bus
master can keep BB asserted after ceasing bus activity, regardless of whether
BR is asserted or deasserted. This is called “bus parking” and allows the
current bus master to reuse the bus without re-arbitration until another device
requires the bus. BB is deasserted by an “active pull-up” method (that is, BB is
driven high and then released and held high by an external pull-up resistor).
BB requires an external pull-up resistor.
BL
Output
Driven high
(deasserted)
Bus Lock—BL is asserted at the start of an external divisible Read-Modify-
Write (RMW) bus cycle, remains asserted between the read and write cycles,
and is deasserted at the end of the write bus cycle. This provides an “early bus
start” signal for the bus controller. BL may be used to “resource lock” an
external multi-port memory for secure semaphore updates. Early deassertion
provides an “early bus end” signal useful for external bus control. If the
external bus is not used during an instruction cycle, BL remains deasserted
until the next external indivisible RMW cycle. The only instructions that assert
BL automatically are the BSET, CLR, and BCHG instructions when they are
used to modify external memory. An operation can also assert BL by setting
the BLH bit in the Bus Control Register.
CAS
Output
Output
Output
Tri-stated
Tri-stated
Tri-stated
Column Address Strobe
When the DSP is the bus master, DRAM uses CAS to strobe the column
address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM
Control Register is cleared, the signal is tri-stated.
BCLK
BCLK
Bus Clock
When the DSP is the bus master, BCLK is active when the OMR[ATE] is set.
When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK
precedes CLKOUT by one-fourth of a clock cycle.
Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the BCLK signal.
Otherwise, the signal is tri-stated.
DSP56301 Technical Data, Rev. 10
1-8
Freescale Semiconductor
FREESCALE [ Freescale ]
