Signals/Connections
DSP56301
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
1
Interrupt
/Mode
Control
Power Inputs :
V
PLL
CCP
4
6
4
2
6
2
V
Internal Logic
Address Bus
Data Bus
CCQ
V
CCA
V
CCD
V
Bus Control
HI32
ESSI/SCI/Timer
CCN
V
CCH
Universal
Bus
Port B
GPIO
V
CCS
PCI Bus
Host
52
1
See Figure 1-2 for a listing of the
Host Interface/Port B Signals
Grounds :
PLL
PLL
Interface
2
GND
P
(HI32) Port
GND
GND
GND
GND
GND
GND
GND
P1
4
Internal Logic
Address Bus
Data Bus
Bus Control
HI32
Q
6
4
2
6
2
A
D
N
H
ESSI/SCI/Timer
S
Port C GPIO
PC[0-2]
PC3
3
Extended Synchronous
Serial Interface Port 0
SC[00-02]
SCK0
SRD0
EXTAL
XTAL
Clock
3
(ESSI0)
PC4
STD0
PC5
CLKOUT
PCAP
PINIT/NMI
PLL
Port D GPIO
PD[0-2]
PD3
PD4
PD5
3
Extended
Synchronous Serial
Interface Port 1
SC[10-12]
SCK1
SRD1
Port A
External
Address Bus
3
(ESSI1)
STD1
24
A[0-23]
D[0-23]
24
4
External
Data Bus
Port E GPIO
PE0
PE1
Serial
RXD
TXD
SCLK
Communications
3
Interface (SCI) Port
AA[0–3]
RAS[0–3]
RD
PE2
External
Bus
WR
BS
TA
BR
Timer GPIO
TIO0
TIO1
Control
TIO0
TIO1
TIO2
4
Timers
TIO2
BG
BB
BL
TCK
TDI
TDO
TMS
TRST
DE
JTAG/OnC
E Port
CAS
BCLK
BCLK
Notes: 1. Power and ground connections are shown for the TQFP package. The MAP-BGA package uses one
for the PLL power input and 44 V pins that connect to an internal power plane. The MAP-
V
CCP
CC
BGA package uses two ground connections for the PLL (GND and GND ) and 36 GND pins that
P
P1
connect to an internal ground plane.
2. The HI32 port supports PCI and non-PCI bus configurations. Twenty-four HI32 signals can also be
configured as GPIO signals (PB[0–23]).
3. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D
GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
4. TIO[0–2] can be configured as GPIO signals.
Figure 1-1. Signals Identified by Functional Group
DSP56301 Technical Data, Rev. 10
1-2
Freescale Semiconductor
FREESCALE [ Freescale ]
