Specifications
Table 2-20. PCI Mode Timing Parameters1
80 MHz
100 MHz
No.
Characteristic10
Symbol
Unit
Min
Max
Min
Max
349 HCLK to Signal Valid Delay—Bussed Signals
350 HCLK to Signal Valid Delay—Point to Point
351 Float to Active Delay
t
2.0
2.0
11.0
12.0
—
2.0
2.0
11.0
12.0
—
ns
ns
ns
ns
ns
ns
ns
ms
μs
ns
ns
ns
ns
VAL
t
VAL(ptp)
t
2.0
2.0
ON
352 Active to Float Delay
t
—
28.0
—
—
28.0
—
OFF
353 Input Set Up Time to HCLK—Bussed Signals
354 Input Set Up Time to HCLK—Point to Point
355 Input Hold Time from HCLK
t
7.0
7.0
SU
t
10.0, 12.0
0.0
—
10.0, 12.0
0.0
—
SU(ptp)
t
—
—
H
356 Reset Active Time After Power Stable
357 Reset Active Time After HCLK Stable
358 Reset Active to Output Float Delay
359 HCLK Cycle Time
t
1.0
—
1.0
—
RST
t
100.0
—
—
100.0
—
—
RST-CLK
RST-OFF
t
40.0
—
40.0
—
t
30.0
11.0
11.0
30.0
11.0
11.0
CYC
360 HCLK High Time
t
—
—
HIGH
361 HCLK Low Time
t
—
—
LOW
Notes: 1. For standard PCI timing, see the PCI Local Bus Specification, Rev. 2.0, especially Chapters 3 and 4.
2. The HI32 supports these timings for a PCI bus operating at 33 MHz for a DSP clock frequency of 56 MHz and above. The DSP
core operating frequency should be greater than 5/3 of the PCI bus frequency to maintain proper PCI operation.
3. HGNT has a setup time of 10 ns. HREQ has a setup time of 12 ns.
359
361
HCLK
360
349
350
OUTPUT
DELAY
351
High
Impedance
OUTPUT
352
INPUT
353
355
354
Figure 2-36. PCI Timing
DSP56301 Technical Data, Rev. 10
2-40
Freescale Semiconductor
FREESCALE [ Freescale ]
