Table of Contents
DSP56301 Features.............................................................................................................................................iii
Target Applications.............................................................................................................................................iv
Product Documentation ......................................................................................................................................iv
Chapter 1
Signals/Connections
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
Power ................................................................................................................................................................1-4
Ground ..............................................................................................................................................................1-4
Clock.................................................................................................................................................................1-5
Phase Lock Loop (PLL)....................................................................................................................................1-5
External Memory Expansion Port (Port A) ......................................................................................................1-6
Interrupt and Mode Control..............................................................................................................................1-9
Host Interface (HI32)......................................................................................................................................1-10
Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-16
Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-18
Serial Communication Interface (SCI) ...........................................................................................................1-19
Timers .............................................................................................................................................................1-20
JTAG/OnCE Interface.....................................................................................................................................1-21
Chapter 2
Specifications
2.1
2.2
2.3
2.4
2.5
Maximum Ratings.............................................................................................................................................2-1
Absolute Maximum Ratings.............................................................................................................................2-2
Thermal Characteristics....................................................................................................................................2-2
DC Electrical Characteristics............................................................................................................................2-2
AC Electrical Characteristics............................................................................................................................2-4
Chapter 3
Chapter 4
Packaging
3.1
3.2
3.3
3.4
TQFP Package Description...............................................................................................................................3-2
TQFP Package Mechanical Drawing..............................................................................................................3-11
MAP-BGA Package Description....................................................................................................................3-12
MAP-BGA Package Mechanical Drawing.....................................................................................................3-23
Design Considerations
4.1
4.2
4.3
4.4
4.5
Thermal Design Considerations........................................................................................................................4-1
Electrical Design Considerations......................................................................................................................4-2
Power Consumption Considerations.................................................................................................................4-3
PLL Performance Issues...................................................................................................................................4-4
Input (EXTAL) Jitter Requirements .................................................................................................................4-4
Chapter A
Index
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
Indicates a signal that is active when pulled low (For example, the RESET pin is active when
low.)
“asserted”
“deasserted”
Examples:
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
Logic State
Signal State
Asserted
Voltage
PIN
V /V
True
IL OL
PIN
PIN
PIN
V
V
/V
False
True
False
Deasserted
Asserted
Deasserted
IH OH
/V
IH OH
V /V
IL OL
Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
DSP56301 Technical Data, Rev. 10
ii
Freescale Semiconductor
FREESCALE [ Freescale ]
