DSP56301 Features
High-Performance DSP56300 Core
• 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-
Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support
under software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes
optimized for DSP applications (including immediate offsets), internal instruction cache
controller, internal memory-expandable hardware stack, nested hardware DO loops, and fast
auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external
accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-
block-transfer interrupts; and triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock
and output clock with skew elimination
• Hardware debugging support including On-Chip Emulation (OnCE™) module, Joint Test Action
Group (JTAG) Test Access Port (TAP)
Internal Peripherals
• 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless
interface to other DSP563xx buses or ISA interface requiring only 74LS45-style buffers
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three
transmitters (allows six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which
peripherals are enabled
Internal Memories
• 3 K × 24-bit bootstrap ROM
• 8 K × 24-bit internal RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
ProgramRAM Instruction Cache
Instruction
Cache
Switch
Mode
X Data RAM Size Y Data RAM Size
Size
Size
4096 × 24 bits
3072 × 24 bits
2048 × 24 bits
1024 × 24 bits
0
2048 × 24 bits
2048 × 24 bits
3072 × 24 bits
3072 × 24 bits
2048 × 24 bits
2048 × 24 bits
3072 × 24 bits
3072 × 24 bits
disabled
enabled
disabled
enabled
disabled
disabled
enabled
enabled
1024 × 24-bit
0
1024 × 24-bit
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
iii
FREESCALE [ Freescale ]
