Specifications
Table 2-8. SRAM Read and Write Accesses3,6 (Continued)
80 MHz
100 MHz
No.
Characteristics
Symbol
Expression1
Unit
Min
Max
Min
Max
115 Address valid to RD
assertion
0.5 × T − 4.0
2.3
—
1.0
8.5
—
ns
ns
C
116 RD assertion pulse width
(WS + 0.25) × T −4.0
11.6
—
—
C
117 RD deassertion to address
not valid
0.25 × T − 2.0 [1 ≤ WS ≤ 3]
1.1
13.6
26.1
—
—
—
0.5
10.5
20.5
—
—
—
ns
ns
ns
C
1.25 × T − 2.0 [4 ≤ WS ≤ 7]
C
2.25 × T − 2.0 [WS ≥ 8]
C
118 TA setup before RD or WR
0.25 × T + 2.0
5.1
0
—
—
4.5
0
—
—
ns
ns
C
4
deassertion
119 TA hold after RD or WR
deassertion
Notes: 1. WS is the number of wait states specified in the BCR.
2. Timings 100, 107 are guaranteed by design, not tested.
3. All timings for 100 MHz are measured from 0.5 · Vcc to 0.5 · Vcc
4. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains active.
5. Timings 110, 111, and 112, are not helpful and are not specified for 100 MHz.
6.
V
= 3.3 V 0.3 V; T = –40°C to +100°C, C = 50 pF
CC J L
100
A[0–23]
AA[0–3]
117
113
116
RD
105
106
119
WR
104
118
TA
Data
In
D[0–23]
Note: Address lines A[0–23] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-12. SRAM Read Access
DSP56301 Technical Data, Rev. 10
2-14
Freescale Semiconductor
FREESCALE [ Freescale ]
