Specifications
2.5.5.2 DRAM Timing
The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based
on the timing in the following tables. For example, the selection guide suggests that four wait states must be used
for 100 MHz operation in Page Mode DRAM. However, using the information in the appropriate table, a designer
could choose to evaluate whether fewer wait states might be used by determining which timing prevents operation
at 100 MHz, by running the chip at a slightly lower frequency (for example, 95 MHz), by using faster DRAM (if it
becomes available), and by manipulating control factors such as capacitive and resistive load to improve overall
system performance.
Note:
This figure should be used for primary selection. For exact
and detailed timings see the following tables.
DRAM type
(tRAC ns)
100
80
70
60
50
Chip frequency
(MHz)
120
40
66
80
100
1 Wait state
2 Wait states
3 Wait states
4 Wait states
Figure 2-14. DRAM Page Mode Wait States Selection Guide
DSP56301 Technical Data, Rev. 10
2-16
Freescale Semiconductor
FREESCALE [ Freescale ]
