Pin Descriptions Grouped by Function
43
Executive Processor The XP’s system interface manages the supervisory controls for the network interfaces, as
System Interface Signals
well as the set of pins that provide interfaces to other components in the system that are
not memories or network interfaces. It is also the primary interface used for initializing the
C-3e NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM
interface signals.
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or
66MHz. The PCI is fully compliant with PCI Specification revision 2.1. Table 15 describes
the PCI signals.
Table 15 PCI Signals
SIGNAL NAME
PIN #
TOTAL TYPE
I/O
SIGNAL DESCRIPTION
PAD0 - PAD31
AB9, AC9, AE9, AF9, AB8, AC8,
AD8, AE8, AF8, AG8, AB7, AC7,
AD7, AE7, AF7, AG7, AB6, AC6,
AE6, AG6, AB5, AC5, AD5, AE5,
AF5, AG5, AB4, AD4, AF4, AG4,
AA3, AB3,
32
PCI
I/O Multiplexed Address/Data Bus. These signals are
multiplexed address and data bits. The C-3e NP
receives addresses as target and drives addresses as
master. It drives the data and receives read data as
master.
PCBEX0 - PCBEX3 AB2, AG3, AF3, AE3
4
1
PCI
PCI
I/O Command byte enables. These signals are
multiplexed command and byte enabled signals.
The C-3e NP receives byte enables as target and drives
byte enables as master.
PPAR
AG1
I/O Parity. This signal carries even parity for AD and CBE#
pins. It has the same receive and drive characteristics
as the address and data bus, except that it is one PCI
cycle later.
PFRAMEX
PTRDYX
PIRDYX
PSTOPX
PDEVSELX
PPERRX
PSERRX
PCLK
AA7
AB1
AC2
AE2
AG2
AC3
AD3
AF1
AE1
AD1
1
1
1
1
1
1
1
1
1
1
PCI
PCI
PCI
PCI
PCI
PCI
PCI
IPD
I/O Cycle frame
I/O Target ready for data transfer
I/O Initiator ready for data transfer
I/O Target transaction stop request
I/O Target device selected
I/O Bus parity error
I/O System error
I
Bus clock
PRSTX
PCI
PCI
I
Bus reset
PREQX
O
Initiator bus request (arbitration)
03
FREESCALE [ Freescale ]
