Pin Descriptions Grouped by Function
39
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
SIGNAL NAME*
CPn+1_3
CPn+1_4
CPn+1_5
CPn+1_6
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
CPn+3_0
CPn+3_1
CPn+3_2
CPn+3_3
CPn+3_4
CPn+3_5
CPn+3_6
PIN #† TOTAL TYPE
I/O
LABEL
TXD(4)
TXD(3)
TXD(2)
TXD(0)
SIGNAL DESCRIPTION
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVTTL
LVTTL
LVTTL
LVTTL
nc
OPU
OPD
OPU
OPU
Transmit Data
Transmit Data
Transmit Data
Transmit Data (ten bits wide, first on wire)
nc
ncPD nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
IPU
IPD
IPU
IPD
IPU
IPU
RCLK
Receive Clock (62.5 MHz)
Receive Data (ten bits wide, last on wire)
Receive Data
RXD(9)
RXD(8)
RXD(7)
RXD(6)
RXD(1)
Receive Data
Receive Data
Receive Data
ncPD nc
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
IPU
IPD
IPU
IPD
IPU
IPU
RCLKN
Receive Clock Inverted
Receive Data
RXD(5)
RXD(4)
RXD(3)
RXD(2)
RXD(0)
Receive Data
Receive Data
Receive Data
Receive Data (ten bits wide, first on wire)
28
TOTAL PINS
*
n can be 0, or 4.
†
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
03
FREESCALE [ Freescale ]
