46
CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 5 PROM Interface Diagram
C-3e Network Processor External Logic
21
0
PROM_ADDR<21:1>
CE
SPDO
SPDI
21
6
1
0
21
21
6 0
Internal Shift
Register
External Shift
Register
0
15
21
PROM_ADDR<21:1>
21
CE
31
16 15
0
PROM _H_Word
PROM _LO_Word
1
16
PROM _Return_Data
PROM Clock Gen.
PROM Sequencer
PROM
SPCLK
SPLD
PROM_Data
The PROM interface operates in the following manner (Note that two accesses are
piplined together to execute one 32-bit fetch). The steps are shown in Figure 6.
1 The PROM_ADDR is loaded into the network processor internal shift register.
2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.
3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register.
4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit
PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift
register.
5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external
presentation register and the first PROM_DATA into the external shift register.
6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network
processor internal shift register.
7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network
processor PROM_RETURN_DATA register and the second PROM_DATA into the
external shift register.
C3EN
FREESCALE [ Freescale ]
