Pin Descriptions Grouped by Function
47
8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the
network processor internal shift register.
9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the
network processor PROM_RETURN_DATA register.
Figure 6 PROM Interface Timing Outline
XP PROM Interface outline
SPLD
‘
A1
A2
A3
D1
A4
D2
A5
SPDTO
D3
SPDTI
XP PROM Interface detail
23
14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
6
7
1
2
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
6
7
8
9
10 11 12 13
SPCLK
SPLD
A1
A2
A3
A4
A
A
A
A
A
A
A
A
A
A
A
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
CE
x
SPDTO
20 19 18 17 16 15 14 13 12 11 10
0
The PROM_ADDR is loaded into the
C-5's internal shift register.
3
5
1
The PROM_ADDR is shifted into
the external shift register.
The PROM_ADDR is loaded into the
external presentation register.
(SPCLK Rising Edge used for shifting)
4
2
The PROM_DATA is
presenting.
The PROM_DATA is loaded into the
external shift register.
D1
D2
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
x
x
x
x
x
x
x
SPDTI
15 14 13 12 11 10
The PROM_DATA is shifted into the C-5's
Internal shift register.
6
8
The PROM_DATA is loaded into the C-5's
internal PROM_RETURN_DATA register.
7
9
03
FREESCALE [ Freescale ]
