Pin Descriptions Grouped by Function
37
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME*
PIN #† TOTAL TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
Table 7 1
LVTTL OPD T_CLK
GMII Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
CPn_1
Table 7 1
LVTTL IPU
TCLKI
MII transmit clock. Transmit data aligned to this clock input from
phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVTTL OPD TXD(0)
LVTTL OPU TXD(1)
LVTTL OPD TXD(2)
LVTTL OPU TXD(3)
LVTTL OPU TX_EN
Transmit Data (byte-wide data, least significant bit)
Transmit Data
Transmit Data
Transmit Data
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
CPn+1_0
CPn+1_1
Table 7 1
Table 7 1
nc
ncPD nc
COL
nc
LVTTL IPU
Collision. Asserted when both RX_DV and TX_EN are valid during
half duplex operation.
CPn+1_2
CPn+1_3
CPn+1_4
CPn+1_5
CPn+1_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVTTL OPD TXD(4)
LVTTL OPU TXD(5)
LVTTL OPD TXD(6)
LVTTL OPU TXD(7)
LVTTL OPU TX_ER
Transmit Data
Transmit Data
Transmit Data
Transmit Data (byte-wide receive data, most significant bit)
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes
transmission of the designated “bad code” in lieu of the normal
encoded data on the twisted pair data.
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
nc
ncPD nc
nc
LVTTL IPU
LVTTL IPD
LVTTL IPU
LVTTL IPD
LVTTL IPU
LVTTL IPU
RCLK
Receive Clock (125MHz)
RXD(0)
RXD(1)
RXD(2)
RXD(3)
RX_DV
Receive Data (byte-wide receive data, least significant bit)
Receive Data
Receive Data
Receive Data
Receive Data Valid. Indicates that there is a receive frame in progress
and that the data present on the RXD signals is valid.
CPn+3_0
CPn+3_1
Table 7 1
Table 7 1
nc
ncPD nc
nc
LVTTL IPU
CRS
Carrier Sense. Indicates traffic is on the link. CRS is asserted when a
non-idle condition is detected on the receive data stream. CRS is
deasserted when an end of frame or idle condition is detected.
03
FREESCALE [ Freescale ]
