Pin Descriptions Grouped by Function
35
10/100 Ethernet (RMII) Configuration
Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
Table 9 10/100 Ethernet Signals
SIGNAL NAME*
CPn_0
PIN #
TOTAL TYPE
I/O
OPD
IPU
LABEL
SIGNAL DESCRIPTION
Table 7
Table 7
1
1
LVTTL
LVTTL
REF_CLK
CRS_DV
Transmit and Receive Clock (50MHz)
CPn_1
Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that
traffic is on the link, and is asserted if the signal is a 1 or an
alternating 1010... RX_DV indicates that a receive frame is in
progress and the data present on the RXD pins is valid. It is
asserted if this signal is a 1 for more than one cycle.
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Table 7
Table 7
Table 7
Table 7
Table 7
1
1
1
1
1
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
OPD
OPU
IPD
TXD(0)
TXD(1)
RXD(0)
RXD(1)
TX_EN
Transmit Data 0 (first on wire)
Transmit Data 1 (second on wire)
Receive Data 0 (first on wire)
Receive Data 1 (second on wire)
IPU
OPU
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
7
TOTAL PINS
*
n can be from 0 to 7. See Table 7.
03
FREESCALE [ Freescale ]
