Freescale Semiconductor, Inc.
5.7.3.8 SINGLE OPERAND INSTRUCTIONS. The single operand instruction table
indicates the number of clock periods needed for the processor to perform the specified
operation using the specified addressing mode. The total number of clock cycles is
outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total
clock cycle number. All timing data assumes two-clock reads and writes.
Instruction
Dn
CEA
Dn
FEA
Dn
FEA
Dn
FEA
Head
Tail
0
Cycles
2(0/1/0)
4(0/1/x)
2(0/1/0)
5(0/1/x)
2(0/1/0)
5(0/1/x)
2(0/1/0)
5(0/1/x)
2(0/1/0)
4(0/1/0)
6(0/1/1)
4(0/1/0)
6(0/1/1)
6(0/1/0)
10(0/1/1)
2(0/1/0)
CLR
0
0
0
0
0
0
0
0
0
2
0
2
2
4
1
0
CLR
2
NEG
NEG
NEGX
NEGX
NOT
NOT
EXT
0
3
0
3
0
3
Dn
Dn
0
NBCD
NBCD
Scc
0
FEA
Dn
CEA
Dn
CEA
FEA
2
0
Scc
2
TAS
0
TAS
0
TST
0
X
= There is one bus cycle for byte and word operands and two bus cycles for long-word
operands. For long-word bus cycles, add two clocks to the tail and to the number of
cycles.
MOTOROLA
MC68340 USER’S MANUAL
5-107
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