Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Port Signals
3.5 Port Signals
The MC68HC912DG128 incorporates eleven ports which are used to
control and access the various device subsystems. When not used for
these purposes, port pins may be used for general-purpose I/O. In
addition to the pins described below, each port consists of a data register
which can be read and written at any time, and, with the exception of port
AD0, port AD1, PE[1:0], RxCAN and TxCAN, a data direction register
which controls the direction of each pin. After reset all general purpose
I/O pins are configured as input.
3.5.1 Port A
Port A pins are used for address and data in expanded modes. In single
chip modes, the pins can be used as general purpose I/O. The port data
register is not in the address map during expanded and peripheral mode
operation. When it is in the map, port A can be read or written at anytime.
Register DDRA determines whether each port A pin is an input or output.
DDRA is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRA makes the corresponding bit in port A
an output; clearing a bit in DDRA makes the corresponding bit in port A
an input. The default reset state of DDRA is all zeros.
When the PUPA bit in the PUCR register is set, all port A input pins are
pulled-up internally by an active pull-up device. PUCR is not in the
address map in peripheral mode.
Setting the RDPA bit in register RDRIV causes all port A outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to Bus Control and
Input/Output.
3.5.2 Port B
Port B pins are used for address and data in expanded modes. In single
chip modes, the pins can be used as general purpose I/O. The port data
register is not in the address map during expanded and peripheral mode
operation. When it is in the map, port B can be read or written at anytime.
MC68HC912DG128 — Rev 3.0
Technical Data
Pinout and Signal Descriptions
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