Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Signal Descriptions
3.4.15 Clock generation module test (CGMTST)
The CGMTST pin (PE6) is the output of the clocks tested when CGMTE
bit is set in PEAR register. The PIPOE bit must be cleared for the clocks
to be tested.
Table 3-2. Signal Description Summary
Pin
Shared
port
Number
112-pin
47
Pin Name
Description
EXTAL
XTAL
-
-
Crystal driver and external clock input pins. On reset all the device clocks
are derived from the EXTAL input frequency. XTAL is the crystal output.
48
An active low bidirectional control signal, RESET acts as an input to
initialize the MCU to a known start-up state, and an output when COP or
clock monitor causes a reset.
RESET
-
46
ADDR[7:0]
DATA[7:0]
PB[7:0]
PA[7:0]
31–24
64–57
External bus pins share function with general-purpose I/O ports A and B.
In single chip modes, the pins can be used for I/O. In expanded modes,
the pins are used for the external buses.
ADDR[15:8]
DATA[15:8]
Data bus control and, in expanded mode, enables the drive control of
external buses during external reads.
DBE
PE7
PE7
36
36
ECLK
Inverted E clock used to latch the address.
CAL is the output of the Slow Mode programmable clock divider,
SLWCLK, and is used as a calibration reference for functions such as
time of day. It is overridden when DBE function is enabled. It always has
a 50% duty.
CAL
PE7
PE6
36
37
CGMTST
Clock generation module test output.
MODB/
IPIPE1,
MODA/
IPIPE0
State of mode select pins during reset determine the initial operating
mode of the MCU. After reset, MODB and MODA can be configured as
instruction queue tracking signals IPIPE1 and IPIPE0 or as general-
purpose I/O pins.
PE6, PE5
37, 38
E Clock is the output connection for the external bus clock. ECLK is used
as a timing reference and for address demultiplexing.
ECLK
PE4
PE3
PE2
PE1
39
53
54
55
Low byte strobe (0 = low byte valid), in all modes this pin can be used as
I/O. The low strobe function is the exclusive-NOR of A0 and the internal
SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin
function TAGLO used in instruction tagging. See Development Support.
LSTRB/
TAGLO
Indicates direction of data on expansion bus. Shares function with
general-purpose I/O. Read/write in expanded modes.
R/W
IRQ
Maskable interrupt request input provides a means of applying
asynchronous interrupt requests to the MCU. Either falling edge-
sensitive triggering or level-sensitive triggering is program selectable
(INTCR register).
MC68HC912DG128 — Rev 3.0
Technical Data
Pinout and Signal Descriptions
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