Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
3.4.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)
These signals are used to track the state of the internal instruction
execution queue. Execution state is time-multiplexed on the two signals.
Refer to Development Support.
3.4.12 Data Bus Enable (DBE)
The DBE pin (PE7) is an active low signal that will be asserted low during
E-clock high time. DBE provides separation between output of a
multiplexed address and the input of data. When an external address is
stretched, DBE is asserted during what would be the last quarter cycle
of the last E-clock cycle of stretch. In expanded modes this pin is used
to enable the drive control of external buses during external reads. Use
of the DBE is controlled by the NDBE bit in the PEAR register. DBE is
enabled out of reset in expanded modes. This pin has an active pull-up
during and after reset in single chip modes.
3.4.13 Inverted E clock (ECLK)
The ECLK pin (PE7) can be used to latch the address for de-
multiplexing. It has the same behavior as the ECLK, except is inverted.
In expanded modes this pin is used to enable the drive control of external
buses during external reads. Use of the ECLK is controlled by the NDBE
and DBENE bits in the PEAR register.
3.4.14 Calibration reference (CAL)
The CAL pin (PE7) is the output of the Slow Mode programmable clock
divider, SLWCLK, and is used as a calibration reference. The SLWCLK
frequency is equal to the crystal frequency out of reset and always has
a 50% duty. If the DBE function is enabled it will override the enabled
CAL output. The CAL pin output is disabled by clearing CALE bit in the
PEAR register.
Technical Data
MC68HC912DG128 — Rev 3.0
Pinout and Signal Descriptions
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