Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Table 3-2. Signal Description Summary
Pin
Number
Shared
port
Pin Name
Description
112-pin
Provides a means of requesting asynchronous nonmaskable interrupt
requests after reset initialization
XIRQ
PE0
-
56
23
During reset, this pin determines special or normal operating mode. After
reset, single-wire background interface pin is dedicated to the
background debug function. Pin function TAGHI used in instruction
tagging. See Development Support.
SMODN/
BKGD/
TAGHI
IX[2:0]
ECS
PK[2:0]
PK7
109-111 Page Index register emulation outputs.
108 Emulation Chip select.
PW[3:0]
PP[3:0]
112, 1–3 Pulse Width Modulator channel outputs.
Slave select output for SPI master mode, input for slave mode or master
mode.
SS
PS7
96
SCK
SDO/MOSI
SDI/MISO
TxD1
PS6
PS5
PS4
PS3
PS2
PS1
PS0
95
94
93
92
91
90
89
Serial clock for SPI system.
Master out/slave in pin for serial peripheral interface
Master in/slave out pin for serial peripheral interface
SCI1 transmit pin
RxD1
SCI1 receive pin
TxD0
SCI0 transmit pin
RxD0
SCI0 receive pin
Pins used for input capture and output compare in the timer and pulse
accumulator subsystem.
IOC[7:0]
PT[7:0] 18–15, 7–4
84/82/80/7
AN1[7:0]
PAD1[7:0] 8/76/74/72/ Analog inputs for the analog-to-digital conversion module 1
70
83/81/79/7
AN0[7:0]
PAD0[7:0] 7/75/73/71/ Analog inputs for the analog-to-digital conversion module 0
69
TxCAN1
RxCAN1
TxCAN0
RxCAN0
SCL
-
102
103
104
105
98
MSCAN1 transmit pin
MSCAN1 receive pin
MSCAN0 transmit pin
MSCAN0 receive pin
-
-
-
I2C bus serial clock line pin
I2C bus serial data line pin
PIB7
SDA
PIB6
99
8–11,
19–22
Key wake-up and general purpose I/O; can cause an interrupt when an
input transitions from high to low or from low to high (KWPJ).
KWJ[7:0]
PJ[7:0]
32–35, Key wake-up and general purpose I/O; can cause an interrupt when an
49–52 input transitions from high to low or from low to high (KWPH).
KWH[7:0]
PH[7:0]
Technical Data
MC68HC912DG128 — Rev 3.0
Pinout and Signal Descriptions
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