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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Pinout and Signal Descriptions  
3.4.5 Nonmaskable Interrupt (XIRQ)  
The XIRQ input provides a means of requesting a nonmaskable interrupt  
after reset initialization. During reset, the X bit in the condition code  
register (CCR) is set and any interrupt is masked until MCU software  
enables it. Because the XIRQ input is level sensitive, it can be connected  
to a multiple-source wired-OR network. This pin is always an input and  
can always be read. There is an active pull-up on this pin while in reset  
and immediately out of reset. The pull-up can be turned off by clearing  
PUPE in the PUCR register. XIRQ is often used as a power loss detect  
interrupt.  
Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ  
must be configured for level-sensitive operation if there is more than one  
source of IRQ interrupt), each source must drive the interrupt input with  
an open-drain type of driver to avoid contention between outputs. There  
must also be an interlock mechanism at each interrupt source so that the  
source holds the interrupt line low until the MCU recognizes and  
acknowledges the interrupt request. If the interrupt line is held low, the  
MCU will recognize another interrupt as soon as the interrupt mask bit in  
the MCU is cleared (normally upon return from an interrupt).  
3.4.6 Mode Select (SMODN, MODA, and MODB)  
The state of these pins during reset determine the MCU operating mode.  
After reset, MODA and MODB can be configured as instruction queue  
tracking signals IPIPE0 and IPIPE1 in expanded modes. MODA and  
MODB have active pull-downs during reset.  
The SMODN pin has an active pull-up when configured as an input. This  
pin can be used as BKGD or TAGHI after reset.  
3.4.7 Single-Wire Background Mode Pin (BKGD)  
The BKGD pin receives and transmits serial background debugging  
commands. A special self-timing protocol is used. The BKGD pin has an  
active pull-up when configured as an input; BKGD has no pull-up control.  
Refer to Development Support.  
Technical Data  
MC68HC912DG128 — Rev 3.0  
Pinout and Signal Descriptions  
For More Information On This Product,  
Go to: www.freescale.com  
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