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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Pinout and Signal Descriptions  
3.4.2 E-Clock Output (ECLK)  
ECLK is the output connection for the internal bus clock. It is used to  
demultiplex the address and data in expanded modes and is used as a  
timing reference. ECLK frequency is equal to 1/2 the crystal frequency  
out of reset. The E-clock output is turned off in single chip user mode to  
reduce the effects of RFI. It can be turned on if necessary. In special  
single-chip mode, the E-clock is turned ON at reset and can be turned  
OFF. In special peripheral mode the E-clock is an input to the MCU. All  
clocks, including the E clock, are halted when the MCU is in STOP  
mode. It is possible to configure the MCU to interface to slow external  
memory. ECLK can be stretched for such accesses.  
3.4.3 Reset (RESET)  
An active low bidirectional control signal, RESET, acts as an input to  
initialize the MCU to a known start-up state. It also acts as an open-drain  
output to indicate that an internal failure has been detected in either the  
clock monitor or COP watchdog circuit. The MCU goes into reset  
asynchronously and comes out of reset synchronously. This allows the  
part to reach a proper reset state even if the clocks have failed, while  
allowing synchronized operation when starting out of reset.  
It is important to use an external low-voltage reset circuit (such as  
MC34064 or MC34164) to prevent corruption of RAM or EEPROM due  
to power transitions.  
The reset sequence is initiated by any of the following events:  
• Power-on-reset (POR)  
• COP watchdog enabled and watchdog timer times out  
• Clock monitor enabled and Clock monitor detects slow or stopped  
clock  
• User applies a low level to the reset pin  
External circuitry connected to the reset pin should not include a large  
capacitance that would interfere with the ability of this signal to rise to a  
valid logic one within nine bus cycles after the low drive is released.  
Technical Data  
MC68HC912DG128 — Rev 3.0  
Pinout and Signal Descriptions  
For More Information On This Product,  
Go to: www.freescale.com  
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