Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
17.13.4 msCAN12 Bus Timing Register 0 (CBTR0)
Bit 7
SJW1
0
6
SJW0
0
5
BRP5
0
4
BRP4
0
3
BRP3
0
2
BRP2
0
1
BRP1
0
Bit 0
BRP0
0
CBTR0
$0102
R
W
RESET
SJW1, SJW0 — Synchronization Jump Width
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 17-4).
Table 17-4. Synchronization jump width
SJW1
SJW0
Synchronization jump width
1 Tq clock cycle
0
0
1
1
0
1
0
1
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
BRP5 – BRP0 — Baud Rate Prescaler
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to Table 17-5.
Table 17-5. Baud rate prescaler
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0 Prescaler value (P)
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
1
2
3
4
:
:
:
:
:
:
:
:
1
1
1
1
1
1
64
NOTE: The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
MC68HC912DG128 — Rev 3.0
Technical Data
MSCAN Controller
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