Freescale Semiconductor, Inc.
MSCAN Controller
17.13.5 msCAN12 Bus Timing Register 1 (CBTR1)
Bit 7
SAMP
0
6
TSEG22
0
5
TSEG21
0
4
TSEG20
0
3
TSEG13
0
2
TSEG12
0
1
TSEG11
0
Bit 0
TSEG10
0
CBTR1
$0103
R
W
RESET
SAMP — Sampling
This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
0 = One sample per bit.
1 = Three samples per bit(1).
TSEG22 – TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point.
Table 17-6. Time segment syntax
SYNC_SEG
System expects transitions to occur on the bus during this period.
Transmit point A node in transmit mode will transfer a new value to the CAN bus at this point.
A node in receive mode will sample the bus at this point. If the three samples per bit option is
Sample point
selected then this point marks the position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in Table 17-7.
Table 17-7. Time segment values
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
TSEG22 TSEG21 TSEG20 Time segment 2
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
0
1
0
1
.
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
.
0
0
.
0
0
.
0
1
.
1 Tq clock cycle
2 Tq clock cycles
.
.
.
.
.
1
1
1
8 Tq clock cycles
.
.
.
.
.
1
1
1
1
16 Tq clock cycles
1. In this case, PHASE_SEG1 must be at least two time quanta.
Technical Data
MC68HC912DG128 — Rev 3.0
MSCAN Controller
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
