Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
The bit time is determined by the oscillator frequency, the baud rate
prescaler, and the number of time quanta (Tq) clock cycles per bit (as
shown above).
Presc value
BitTime = ------------------------------------------ • number Þ of Þ TimeQuanta
f
CGMCANCLK
NOTE: The CBTR1 register can only be written if the SFTRES bit in CMCR0 is
set.
17.13.6 msCAN12 Receiver Flag Register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by
writing a 1 to the corresponding bit position. A flag can only be cleared
when the condition which caused the setting is no more valid. Writing a
0 has no effect on the flag setting. Every flag has an associated interrupt
enable flag in the CRIER register. A hard or soft reset clears the register.
Bit 7
WUPIF
0
6
RWRNIF
0
5
TWRNIF
0
4
RERRIF
0
3
TERRIF
0
2
BOFFIF
0
1
OVRIF
0
Bit 0
RXF
0
CRFLG
$0104
R
W
RESET
WUPIF — Wake-up Interrupt Flag
If the msCAN12 detects bus activity while in SLEEP Mode, it sets the
WUPIFflag. If not masked, a Wake-Up interrupt is pending while this
flag is set.
0 = No wake-up activity has been observed while in SLEEP Mode.
1 = msCAN12 has detected activity on the bus and requested
wake-up.
RWRNIF — Receiver Warning Interrupt Flag
This flag is set when the msCAN12 goes into warning status due to
the Receive Error counter (REC) exceeding 96 and neither one of the
Error interrupt flags or the Bus-Off interrupt flag is set(1). If not
masked, an Error interrupt is pending while this flag is set.
0 = No receiver warning status has been reached.
1 = msCAN12 went into receiver warning status.
1. Condition to set the flag: RWRNIF = (96 < REC ≤ 127) & RERRIF& TERRIF & BOFFIF
MC68HC912DG128 — Rev 3.0
Technical Data
MSCAN Controller
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