Freescale Semiconductor, Inc.
MSCAN Controller
17.13.3 msCAN12 Module Control Register (CMCR1)
Bit 7
0
6
0
5
0
4
0
3
0
2
LOOPB
0
1
WUPM
0
Bit 0
CLKSRC
0
CMCR1
$0101
R
W
RESET
0
0
0
0
0
LOOPB — Loop Back Self Test Mode
When this bit is set the msCAN12 performs an internal loop back which
can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). The
msCAN12 behaves as it normally does while transmitting and treats its
own transmitted message as a message received from a remote node.
In this state the msCAN12 ignores the bit sent during the ACK slot of
the CAN frame Acknowledge field to ensure proper reception of its
own message. Both transmit and receive interrupts are generated.
0 = Normal operation
1 = Activate loop back self test mode
WUPM — Wake-Up Mode
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see Programmable
Wake-Up Function).
0 = msCAN12 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
1 = msCAN12 will wake up the CPU only in the case of dominant
pulse on the bus which has a length of at least approximately
Twup
.
CLKSRC — msCAN12 Clock Source
This flag defines which clock source the msCAN12 module is driven
from (only for system with CGM module; see Clock System, Figure
17-7).
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
ECLK.
NOTE: The CMCR1 register can be written only if the SFTRES bit in CMCR0 is
set.
Technical Data
MC68HC912DG128 — Rev 3.0
MSCAN Controller
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