Freescale Semiconductor, Inc.
Inter-IC Bus
IBSR — IIC Bus Status Register
$00E3
Bit 7
TCF
1
6
IAAS
0
5
IBB
0
4
IBAL
0
3
0
0
2
SRW
0
1
IBIF
0
Bit 0
RXAK
0
RESET:
This status register is read-only with exception of bit 1 (IBIF) and bit 4
(IBAL), which are software clearable
TCF — Data transferring bit
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the 9th clock of a byte transfer.
0 = Transfer in progress
1 = Transfer complete
IAAS — Addressed as a slave bit
When its own specific address (IIC Bus Address Register) is matched
with the calling address, this bit is set. The CPU is interrupted
provided the IBIE is set. Then the CPU needs to check the SRW bit
and set its Tx/Rx mode accordingly. Writing to the IIC Bus Control
Register clears this bit.
0 = Not addressed
1 = Addressed as a slave
IBB — IIC Bus busy bit
This bit indicates the status of the bus. When a START signal is
detected, the IBB is set. If a STOP signal is detected, it is cleared.
0 = Bus is idle
1 = Bus is busy
IBAL — Arbitration Lost
The arbitration lost bit (IBAL) is set by hardware when the arbitration
procedure is lost. Arbitration is lost in the following circumstances:
1. SDA sampled as low when the master drives a high during an
address or data transmit cycle.
2. SDA sampled as a low when the master drives a high during the
acknowledge bit of a data receive cycle.
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
Technical Data
MC68HC912DG128 — Rev 3.0
Inter-IC Bus
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