Freescale Semiconductor, Inc.
Inter-IC Bus
Table 15-1. IIC Tap and Prescale Values
IBC2-0
(bin)
SCL Tap SDA Tap
IBC5-3
(bin)
scl2tap
(clocks)
tap2tap
(clocks)
(clocks)
(clocks)
000
001
010
011
100
101
110
111
5
6
1
1
2
2
3
3
4
4
000
001
010
011
100
101
110
111
4
4
1
2
7
6
4
8
6
8
9
14
30
62
126
16
32
64
128
10
12
15
The number of clocks from the falling edge of SCL to the first tap
(Tap[1]) is defined by the values shown in the scl2tap column of Table
15-1, all subsequent tap points are separated by 2IBC5-3 as shown in
the tap2tap column in Table 15-1. The SCL Tap is used to generated
the SCL period and the SDA Tap is used to determine the delay from
the falling edge of SCL to SDA changing, the SDA hold time.
The serial bit clock frequency is equal to the CPU clock frequency
divided by the divider shown in Table 15-2. The equation used to
generate the divider values from the IBFD bits is:
SCL Divider = 2 x ( scl2tap + [ ( SCL_Tap -1 ) x tap2tap ] + 2 )
The SDA hold delay is equal to the CPU clock period multiplied by the
SDA Hold value shown in Figure 15-2. The equation used to generate
the SDA Hold value from the IBFD bits is:
SDA Hold = scl2tap + [ ( SDA_Tap - 1 ) x tap2tap ] + 3
Technical Data
MC68HC912DG128 — Rev 3.0
Inter-IC Bus
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